Jitter on Chassis With Timing and Synchronization Upgrade

Updated Feb 25, 2021

Reported In

Other

NI PXIe chassis with Timing and Synchronization Upgrade

Issue Details

  • When I am running LabVIEW VI in Phar Lap ETS PXIe controller on PXIe chassis with Timing & Synchronization (T&S) Upgrade, I am seeing jitter on the loop rate.
  • When I deploy the VeriStand project running in Phar Lap ETS PXIe controller to PXIe chassis with T&S Upgrade, I am seeing jitter in Actual Loop Rate.

Solution

NI has discovered that the USB host controller on the T&S Upgrade module is firing off interrupts constantly, causing the jitter in the timed loop. New version of firmware has been released to disable the USB on the T&S Upgrade module. Download the BIOS and follow the instruction in the Readme to update the BIOS :
This issue does not affect PXIe controller running NI Linux RT.

Additional Information

NI will remove support for Phar Lap for PXI in the NI 2022 Software Release. For more information, please see the Phar Lap RT OS EOL Road Map .

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