LabVIEW 64-bit supports the FPGA Host Communication interface on Windows 64-bit systems only. This means that you are able to communicate with the FPGA target from a Host VI using the FPGA Interface palette (shown below).
Up to LabVIEW 2017 SP1 you could not
use the module with LabVIEW 64-bit
, as LabVIEW FPGA Module 2017 and earlier came in 32 bit. A 64-bit version of the LabVIEW FPGA Module was released in 2018.Note:
The 64-bit version of the FPGA Module 2018 only supports a subset of the hardware
supported in the 32-bit version of the module.
The host VI may be targeting a local RIO device or a remote RIO device over the network. The Host Communication in LabVIEW 64-bit has the following limitations, if a version without FPGA 64-bit is used:
- Development or compilation of FPGA VIs is not supported. The following project items cannot be added to the LabVIEW project:
- Real-Time or CompactRIO Targets
- FPGA Targets or Chassis items
- C Series Modules
- Development or compilation of FPGA VIs is not supported.
- Additionally, interaction with the project items listed above will be disabled if an existing project with these items is opened in LabVIEW 64-bit.
Follow these steps to create a Host VI that will communicate with your FPGA target:Note:
Generally, LabVIEW Projects and VIs are inter-operable across bitness of the same version of LabVIEW. However, on versions prior to 2018 the Real-time and FPGA development features will be disabled from within the project.
- In the Project Explorer window right-click My Computer and select New»VI:
- Open the block diagram of the Host VI and place an Open FPGA Reference VI onto the block diagram:
- Open a reference to a precompiled LabVIEW FPGA bitfile by right-clicking the Open FPGA Reference VI and selecting Configure Open FPGA VI Reference:
- Connect a RIO Resource name constant to the resource name terminal of the Open FPGA Reference VI.
- From the drop-down menu of the RIO Resource name constant select your FPGA target by clicking the Browse button:
- To read and write data from and to the FPGA target, use FPGA Read/Write Control or DMA FIFO as you would in the LabVIEW FPGA 32-bit development environment:
- At the end of your VI add the Close FPGA VI Reference function to close the reference to the FPGA VI and, optionally, reset its execution.