Add PXIe-6569 Socketed CLIP to a Custom LabVIEW FPGA Project

Updated Sep 23, 2026

Reported In

Hardware

  • PXIe-6569

Software

  • LabVIEW FPGA Module

Driver

  • FlexRIO

Issue Details

I am developing an FPGA application for an NI PXIe-6569 using LabVIEW FPGA Module 2024 Q3. I can successfully build the .lvbitx file on one development system, but when I open the same .lvproj on other computers, the FPGA Main.vi appears broken because the PXIe-6569 Socketed CLIP is unavailable.
I observed that:
  • The PXIe-6569 IO Node is greyed out or broken.
  • The file Ni6569BasicClip.xml is missing.
  • The NI 6569 directory is not present under the FlexRIO installation folders.
  • Reinstalling NI FlexRIO software does not restore the missing CLIP resources.
  • The issue is reproducible on multiple development systems.
  • I cannot build FPGA bitfiles because the required CLIP cannot be selected.

Solution

The PXIe-6569 Socketed CLIP resources are packaged with the PXIe-6569 sample projects and are not automatically installed in a location that is discoverable by newly created FPGA projects.
To make the PXIe-6569 Socketed CLIP available in a custom project:
  1. Locate the PXIe-6569 sample project directory:
    C:\Program Files\NI\LVAddons\flexrioii\1\ProjectTemplates\Source\FlexRIO\NI6569\
  2. Copy the Socketed CLIPs folder from the sample project directory.
  3. Paste the Socketed CLIPs folder into the same directory as the .lvproj file.
  4. Open the LabVIEW FPGA project.
  5. Open the IO Module Socket Properties configuration page.
  6. Select the desired PXIe-6569 Socketed CLIP.
  7. Recompile the FPGA VI if required.
R&D validated this workflow and confirmed that the Socketed CLIP can be successfully selected and used within a custom FPGA project after the resources are copied locally.
Additionally, R&D confirmed the following:
  • The Getting Started FlexRIO Integrated IO.vi template is not required for PXIe-6569 development.
  • All functionality provided by the sample project can be recreated in a custom LabVIEW FPGA project.
  • The sample project primarily serves as a reference implementation.
  • No unique initialization or configuration steps are performed by the sample project that cannot be implemented manually.

Additional Information

The observed behavior occurs because PXIe-6569 Socketed CLIP resources are distributed with the sample projects rather than being installed into a globally discoverable location for all new FPGA projects. As a result, FPGA projects created from scratch may not automatically expose the expected PXIe-6569 CLIP options until the required resources are copied into the project directory.

Other Support Options

Ask the NI Community

Collaborate with other users in our discussion forums



Request Support from an Engineer

A valid service agreement or active software subscription may be required, and support options vary by country.