Solution
The Engine Simulation Toolkit (EST) Custom Device is an asynchronous Custom Device that utilizes a Timed Loop to ensure that the simulated processes execute deterministically. Occasionally, that Timed Loop may be scheduled on core 0 of your Real-Time Controller's CPU. Core 0 is also used to execute hardware interrupts that the VeriStand Engine's Primary Control Loop uses to trigger iterations to start. So when the EST Custom Device runs on Core 0, it can preempt the hardware interrupts from firing, causing the PCL iteration to be delayed.
To fix this, try these options:
- If possible, run your PCL at a slower rate so that there is additional time allowed for both the EST Custom Device and PCL to finish in time.
- The EST Custom Device supports manual processor assignment and decimation. You can manually assign it to run on a different core than CPU0 so that it does not interfere with the interrupts. For example, if you have a 4-core RT Controller, you could manually assign it to run on CPU3. If you don't need the EST Custom Device to run every iteration of the PCL, you could also define a higher decimation factor.
