cRIO-905x FPGA Compilation Fails With Error Place 30-99

Updated Aug 13, 2026

Reported In

Hardware

  • cRIO-9057

Software

  • LabVIEW FPGA Module
  • LabVIEW FPGA Compilation Tool for Vivado 2019.1

Issue Details

I am compiling an FPGA VI for a cRIO-905x target using Vivado 2019.1. The FPGA application contains an IP Integration Node that imports third-party VHDL. The FPGA compilation fails during the placement phase and the bitfile is not generated.
 
The compilation reports the following error:
 
LabVIEW FPGA: The compilation failed due to a Xilinx error.
 
ERROR: [Place 30-99] Placer failed with error:
'Implementation Feasibility' check failed, Please see the previously displayed individual error or warning messages for more details.'
 
 
 

Solution

The cRIO-905x FPGA has limited FPGA resources. When an IP Integration Node imports third-party VHDL, the default implementation settings may not provide sufficient placement optimization, causing the compilation to fail during the placement phase with a Place 30-99 error.
 
Configure the FPGA compilation with the following Xilinx options:
 
Implementation Strategy: Custom
Design Optimization Directive: Explore with remap
Placement Directive: Extra post-placement optimization
Physical Design Optimization Directive: Aggressively explore
Routing Directive: Explore
 
These settings increase optimization effort and can improve placement results on resource-constrained cRIO-905x FPGA targets.

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