Solution
The observed behavior is generally expected and does not indicate a defect.
DAQmx timestamps and the host system clock belong to different time domains. If these timebases are not synchronized to a common reference, their offset will gradually change over time due to small frequency differences between the clocks.
The presence of a PXIe‑6674T can improve the accuracy and stability of the DAQ timing reference. As a result, the frequency difference between the DAQ clock and the host PC clock may become more apparent, causing the timestamp-to-system-time offset to grow more noticeably over long acquisition periods.
A recommended architecture is to use a PXIe‑6683H as the absolute time reference and distribute that timing source throughout the PXI system.
- Synchronize the PXIe‑6683H to GPS or IEEE‑1588/PTP.
- Route the PXIe‑6683H Clock Out signal to the PXIe‑6674T Clock In.
- Configure the PXIe‑6674T to PLL‑lock to that reference.
- Use the PXIe‑6674T to drive PXI_CLK10_IN.
- Configure the DAQ device RefClk.Src to PXIe_CLK100 or PXI_CLK10.
By doing so, all DAQ timing resources are derived from a common, high‑stability reference clock, significantly reducing clock drift within the measurement system.
While this approach may not completely eliminate differences between DAQ time and host system time, it is the recommended method for minimizing long‑term timing drift and achieving the most stable timing architecture.