How to Fix Aurora Example Compilation Error in 659XR_GenerateVHDL.vi

This article explains how to resolve the FPGA compilation error that can occur when compiling Aurora example projects for NI High-Speed Serial (HSS) devices, including the NI PXIe-6592R, NI PXIe-6591R, and NI PXIe-7902R, in LabVIEW FPGA 2023 Q3 or later.You may encounter this issue while generating intermediate FPGA files or building a bitfile. The compilation stops during VHDL generation before the Vivado compilation stage starts and displays the following error:

An internal software error has occurred. Please contact National Instruments technical support at ni.com/support with the following information:

Set Permissions in 659XR_GenerateVHDL.vi:3340001
-> niFpgaTopLevelGenCallTargetSpecificVI.vi
-> niFpgaHandleConstraintsAndMiscFPGAFiles.vi
-> niLvFpgaTopModGen.vi
-> niLvFpgaTopModGen.vi.ProxyCaller

This procedure applies to systems using NI High Speed Serial Instruments Driver (nihss) 2023 Q3 or later.

Option 1: Run LabVIEW as an Administrator

1. Close all instances of NI LabVIEW.

2. Open the Windows Start menu.

3. Right-click the LabVIEW shortcut.

4. Select Run as administrator.

5. Open your Aurora example project or FPGA project.

6. Build the FPGA bitfile again.

Running LabVIEW with elevated permissions allows the FPGA code generation process to update files located under: "C:\Program Files\NI\LVAddons\".

If Option 1 fails proceed with Option 2 as mentioned below:

After completing one of these procedures:

• The Aurora example FPGA project generates VHDL successfully.
• FPGA compilation progresses to the Vivado compilation stage.
• The Set Permissions in 659XR_GenerateVHDL.vi:3340001 error no longer occurs.

Next Steps

If FPGA compilation progresses beyond VHDL generation but subsequently fails:

1. Verify all Socketed CLIP configurations.
2. Review any custom IP integration used by the project.
3. Examine the Vivado compilation log for synthesis or implementation errors unrelated to this permission issue.