Solution
Configure the IP Integration Node settings to match the timing and numeric representation expected by the VHDL.
The IP Integration Node configuration includes clock and enable signals, reset behavior, and IP terminal data types.
If these settings do not match the VHDL design, the IP may compile successfully but the output may not update as expected.
Complete the following checks in the IP Integration Node Properties dialog box.
1. Configure the clock and enable signals.
On the Clock and Enable Signals page, select the VHDL clock signal as the IP Clock Signal.
If the VHDL includes an enable input, select the corresponding enable signal under IP Enable Signal(s).
For example, if the VHDL uses clk as the clock input and clk_enable as the enable input, configure clk as the clock signal and select clk_enable as the enable signal.
Figure 1. Clock and enable signal configuration in the IP Integration Node. In this example, the clock signal is set to clk, No Derived Clock is selected, and clk_enable is selected as the enable signal.
2. Configure the reset signal and reset behavior.
On the Reset Signals and Behavior page, select the reset signal that matches the VHDL design.
If the reset is synchronous, select it under Synchronous reset signal(s).
Configure the asynchronous reset option only if the VHDL uses an asynchronous reset signal.
For example, if the VHDL uses reset as a synchronous reset signal, select reset under Synchronous reset signal(s) and configure the reset behavior accordingly.
Figure 2. Reset signal settings for the IP Integration Node. This example uses reset as the synchronous reset signal, No Asynchronous Reset, one reset cycle, and reset Before first call.
3. Configure the IP terminal data types.
On the IP Terminals page, select each VHDL port and configure the LabVIEW FPGA Data Type to match the numeric representation expected by the VHDL.
A VHDL port declared as std_logic_vector does not by itself indicate whether the value is fixed-point, integer, or single-precision floating-point.
The correct LabVIEW FPGA terminal data type depends on how the VHDL was generated.
For example, if the VHDL expects a Single-Precision Floating-Point bit representation, configure the corresponding input and output terminals as Single-Precision Floating-Point.
If the VHDL expects a fixed-point bit representation, configure the corresponding terminals as Fixed-Point and match the fixed-point settings used by the VHDL.
Figure 3. Terminal data type settings for the IP Integration Node. Set each terminal data type according to the corresponding VHDL port definition, such as SGL.
4. Update connected FPGA VI and host or RT VI objects as needed.
After changing the IP terminal data type, check the controls, indicators, constants, and wires connected to the affected terminal.
If the FPGA VI or host/RT VI has a broken run arrow, or if coercion dots appear on wires connected to the IP Integration Node, update the connected objects to match the IP terminal data type.
This helps avoid unintended type conversion between the LabVIEW FPGA diagram and the imported VHDL IP.
5. Recompile and test the FPGA VI.
After updating the IP Integration Node configuration and connected LabVIEW objects, recompile the FPGA VI and verify whether the output terminal updates as expected.
If the issue remains, validate the VHDL behavior outside of LabVIEW FPGA or review the VHDL generation report to confirm the expected numeric representation of each top-level port.