Can the Guarding Capability of the NI PXIe-4190 Eliminate the Crosstalk Caused by the Mems Wafer During Parallel Testing?

We intend to use the NI PXIe-4190 to perform parallel measurements (simultaneous multi-die testing) on a MEMS wafer. However, the DUT structure presents significant challenges for parallel configurations due to the following reasons:

• The substrates of adjacent MEMS dies are interconnected through a continuous substrate resistance network, without electrical isolation between dies.

• During parallel testing, when multiple PXIe-4190 channels stimulate adjacent dies simultaneously, signals from one channel (e.g., Channel 1) can couple into another channel (e.g., Channel 2) through the shared substrate resistance network. This undesired coupling (crosstalk) can lead to signal interference and potentially corrupt the measurement results.

Given this condition, we would like to understand whether the Guarding (driven guard) capability of the NI PXIe-4190 is sufficient to effectively isolate or suppress this leakage path during simultaneous parallel measurements.

Additionally, are there any recommended hardware configurations or design approaches—such as specific wiring methods, buffering strategies, or active guarding techniques—that would help mitigate this type of substrate-induced crosstalk in this topology?

We cannot guarantee complete isolation of substrate leakage in this scenario. Therefore, the most practical approach is to optimize the test setup as much as possible and rely on measurement results to determine whether the residual coupling is acceptable.

To maximize the effectiveness of the PXIe-4190’s active guarding, the following best practices are recommended:

1. Cable Selection

• Use high-quality triaxial cables to ensure consistent guarding throughout the entire signal path.
• Avoid coaxial cables, as they lack the intermediate guard conductor required for active guarding.

2. Probe Card Design

• Incorporate guard traces into the probe card layout, routing them close to the signal lines.
• These guard traces should be actively driven at the same potential as the signal to minimize leakage currents.
• For MEMS wafers with shared substrates, ensure that DUT (Device Under Test) connections are carefully optimized to reduce leakage paths.

3. Measurement Setup

• Perform open and short compensation to account for stray admittance and improve measurement accuracy.
• Apply appropriate measurement settings (e.g., Power Line Cycle, PLC) to reduce noise and enhance repeatability.

4. Validation

• Conduct both simulations and experimental measurements to verify the effectiveness of guarding in the specific test setup.
• For MEMS wafers without substrate isolation, special attention should be given to evaluating the impact of residual coupling.