Solution
Use a dedicated reference signal as the digital start trigger when the acquisition must begin from the same signal phase or defined timing reference. The external sample clock defines when samples are taken, but it does not guarantee that each repeated acquisition starts from the same signal phase or timing reference point.
To isolate the cause of the apparent phase offset or different start position, verify the relationship between the digital start trigger, the external sample clock timing, and the first valid sample clock edge after the trigger.
Check the following items:
- Check the idle state of the external sample clock before the task starts, to ensure that the first valid sample clock edge after the digital start trigger is the edge expected by the application.
- Check the selected digital start trigger edge, such as Rising Edge or Falling Edge, to determine whether the acquisition reference changes when a different trigger edge is used.
- Check whether the first valid sample clock edge after the trigger corresponds to the expected signal phase or timing reference point.
- Check the external clock signal quality, including pulse width, jitter, noise, missing pulses, unexpected pulses, or unstable edges.
Use an oscilloscope or equivalent measurement tool to observe the PFI signal before the task starts, at the trigger edge, at the first sample clock edge after the trigger, and during steady-state operation. Use this measurement to confirm both the trigger-to-clock timing relationship and the external clock signal quality.
If the waveform shift changes when the digital start trigger edge is changed, the behavior is likely related to the trigger-to-sample-clock edge relationship. If the shift changes with external clock frequency, pulse width, jitter, missing pulses, or unexpected edges, the behavior may be related to the external clock signal quality or timing stability.
If a separate reference signal is available, such as an index, home, synchronization, or one-pulse-per-cycle signal, use it as the digital start trigger. Use the external sample clock to define the sampling interval after that reference point.
If a separate reference signal is not available, acquire a longer continuous waveform and perform software-based alignment or segmentation after acquisition. This can help avoid ambiguity caused by repeatedly starting and stopping a finite acquisition while the external clock timing or signal state is changing.
For troubleshooting, compare the following combinations:
- Idle Low with Rising Edge trigger
- Idle Low with Falling Edge trigger
- Idle High with Rising Edge trigger
- Idle High with Falling Edge trigger
Use the comparison results to determine whether the apparent phase offset follows the selected trigger edge, the first valid sample clock edge, or variations in the external clock signal.