How To Utilize Xillinx IP In LabVIEW FPGA

With the deprecation of the Xilinx IP palette in LabVIEW FPGA 2027 Q1, users who need Xilinx IP in their FPGA designs should configure IP directly in Vivado and import the resulting files into LabVIEW FPGA. This guide walks through that workflow using .xci files however those can also be synthesized into edif or .dcp netlist files and similarly imported.

Prerequisites:

• Xilinx Vivado installed on your machine. The version must match the Vivado version used by the LabVIEW FPGA compile worker for your LabVIEW release. A version mismatch can cause synthesis failures or incompatible IP.
• LabVIEW FPGA with a supported RIO or FPGA target in your project.
• Know the FPGA part number for your NI hardware target. You can find this by right clicking on your LabVIEW FPGA target and selecting "Properties" in the LabVIEW FPGA target properties, in the NI hardware documentation, or in the call to synth_design when building a bitfile for a particular target.

1.Create a Vivado Project

You need a Vivado project that targets the same FPGA part as your NI hardware so that the IP catalog shows only compatible IP.

• Launch Vivado

• Select Create Project from the Quick Start panel

• Choose RTL Project. You can check Do not specify sources at this time since the project is only used for IP configuration

• On the Default Part page, select the FPGA part that matches your NI target (e.g., xcvu11p-flgb2104-2-e for the PXIe-7903).

• Finish the wizard. Vivado opens the project.

2. Browse the IP Catalog

• In the Vivado Flow Navigator (left sidebar), under PROJECT MANAGER, click IP Catalog.
• The IP Catalog panel opens, organized in a tree by category (e.g., Basic Elements, Communication & Networking, Math Functions, DSP, Memory & Storage Controllers, etc.).
• Use the Search bar at the top of the IP Catalog to find specific IP by name or keyword (e.g., "FIFO", "FIR Compiler", "Block Memory Generator", "AXI DMA").
• You can filter by Supported Devices, Vendor, or Status (Production, Beta, Deprecated) using the filter controls.

3.Configure and Customize IP

• Double-click an IP core in the catalog to open its customization dialog.
• The customization GUI lets you set parameters specific to that IP.

• The IP Symbol view on the left side of the dialog shows the port interface that will be generated, this is what you will connect to in LabVIEW FPGA.
• Set the Component Name to something unique and descriptive.
• Click OK when done configuring the IP.
• Vivado prompts you to Generate Output Products. Click Generate.

After generation, the IP output products are located under your Vivado project directory, typically:

4.Option A: Import via .xci File

The .xci file is the recommended approach when you want LabVIEW FPGA and the compile worker to synthesize the IP as part of the FPGA compile. The compile worker invokes Vivado to process the xci file, so the IP is synthesized with settings matching the rest of your design.

• 4A.1 Using the IP Integration Node (IPIN)

• • In your LabVIEW FPGA block diagram, drop an IP Integration Node from the palette.

• • Right-click the IP Integration Node and select Configure… (or double-click it).
  • In the configuration dialog, press the Add Synthesis File... button and add the .xci file.

• • Complete the rest of the wizard.

• 4A.2 Using CLIP (Component-Level IP)

You can also integrate the IP at the CLIP level, perhaps because it connects to physical I/O or because you are using the IP in a larger HDL module. You can reference the xci file in your CLIP XML declaration similar to other files. You can also use the CLIP Wizard to create the XML declaration:

5.Option B: Import a Synthesized Netlist (edif or dcp)

A .dcp (Design Checkpoint) or edif file contains the fully synthesized netlist of the IP. This approach is useful when:

• • You want to avoid having the compile worker re-synthesize the IP (faster compile times for large IP).
  • You run into issues importing the xci file

• 5.1 Generate the DCP in Vivado

If Vivado did not automatically produce a .dcp during output product generation:

• In the Vivado Sources window, right-click your IP instance.
• Select Generate Output Products….

• Select Out-of-Context (OOC) synthesis.
• After generation completes, the .dcp file is generated.
• If you want an edif file, at this point you can File -> Export -> Export Netlist

And then ensure the edif option is selected:

If you have additional HDL surrounding the IP:

• Run Synthesis on your Vivado project (or just the IP).
• After synthesis, open the synthesized design.
• Use File > Checkpoint > Write… to save a .dcp file.

Note: this is also a way to integrate SystemVerilog IP into LabVIEW FPGA.

• 5.2 Import a netlist into LabVIEW FPGA

• • The netlist file can then be used with the IP Integration Node or CLIP in a similar manner to the xci file, add it as a source file in the configuration.
  • If using the IP Integration Node, you will need a simulation model. The option to use LabVIEW to generate a post synthesis simulation model is convenient:

Next Steps

7. Tips and Best Practices

• Match Vivado versions. The Vivado version you use to configure IP must match the version used by the LabVIEW FPGA compile worker. Using a newer Vivado to generate the xci than the compile worker expects can cause errors.
• Version-control the xci file. The .xci file is a text (XML/JSON) file that captures all IP configuration parameters. Check it into source control so IP configuration is reproducible.
• Keep IP output products regenerable. You generally do not need to version-control the entire IP output directory, only the .xci file and any other files considered 'source'. The compile worker regenerates output products from the xci.
• Part compatibility. If your Vivado project targets a different FPGA part than your NI hardware, the IP may fail to synthesize or may be sub-optimal. Always create the Vivado project with the correct part.
• AXI interfaces. Many Xilinx IP cores use AXI bus interfaces. If the IP has an AXI interface, you will need to provide AXI bus logic in an HDL or G wrapper.
• Upgrading IP for new Vivado versions. When LabVIEW upgrades its Vivado version, you may need to open your xci file in the new Vivado, let it upgrade the IP, and re-export the xci/dcp. Vivado's report_ip_status Tcl command can identify IP that needs upgrading.
• Tcl-based IP creation (advanced). For repeatable or scripted workflows, you can create and configure IP entirely via Vivado Tcl commands instead of the GUI.