Solution
The Chassis Master Hardware Synchronization Device defines which hardware module is responsible for distributing the synchronization clock across the PXI chassis backplane. This device must be capable of driving backplane clocks, such as an NI DAQ device with analog input or output channels, an NI FPGA device, or a timing and synchronization module. In a typical setup, this device drives the RTSI 0 or equivalent backplane clock line to synchronize all I/O devices in the chassis.
The Clock Source defines where the selected Chassis Master Hardware Synchronization Device obtains its reference clock. When an internal clock is used, the device relies on its onboard oscillator. When an external clock is required, the Clock Source can be set to a PFI line, such as PFI0, which configures the selected DAQ or timing module to accept an external reference clock on that input.
Using an external clock on a PFI line is supported as long as the selected Chassis Master Hardware Synchronization Device has analog input capability and can drive backplane clocks. The external signal must meet the electrical and timing requirements of the device, such as TTL voltage levels and supported frequency ranges, as specified in the hardware documentation. When properly configured, the external clock received on the PFI line becomes the reference clock that the chassis master distributes to all synchronized devices in the PXI chassis.
For example, to synchronize a PXI chassis using an external clock, the configuration in VeriStand would set the Chassis Master Hardware Synchronization Device to a DAQ module such as a PXIe‑6363 and set the Clock Source to PFI0. An external 5 V TTL clock signal is then connected to the selected PFI line, allowing the chassis to synchronize using that external reference.