Why Veristand PCL Cannot be Set to 500Hz When Using a 1kHz External Clock?

Updated May 7, 2026

Reported In

Software

  • VeriStand

Issue Details

I am using an external clock of 1kHz as the clock source in Veristand and I set the PCL rate to 500Hz. When executing, I noticed that the PCL rate is running at 1kHz instead of 500Hz. 

Why is this happening? Is this expected?

Solution

This is expected as the PCL is acting like the LabVIEW timed loop where the rate is running at the configured clock source.

If you would like to decrease the PCL rate using the external clock, please decrease the external clock rate or use a hardware divider to divide the clock rate.

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