Issue Details
Users of the PXIe‑6569 may encounter non‑deterministic or variable data latency when measuring the timing relationship between an input clock edge and the corresponding data output. Observed latency values may vary from acquisition to acquisition (for example, measurements differing by ~1.6 ns or ~3.2 ns), which can appear as inconsistent FIFO or clock‑to‑data behavior.
This behavior is most commonly reported when the PXIe‑6569 is used in custom CLIP implementations or in applications that require fixed, cycle‑accurate, or bit‑to‑bit deterministic latency. In such use cases, customers may expect a constant alignment between specific data bits (for example, bit 0 to bit 0) across clock cycles, which the PXIe‑6569 does not guarantee.