Send More Than 8 Bits of Serial Data Using NI LabVIEW FPGA

Overview:

Standard NI serial hardware modules are limited to a maximum of 8 data bits per serial frame. This is a fixed hardware constraint and cannot be changed through software configuration.

If your application requires transmitting or receiving more than 8 bits per frame, you can implement a custom serial protocol on an FPGA target using digital I/O lines. CompactRIO controllers and PXIe FPGA modules both support this approach. Because the FPGA provides direct, cycle by cycle control over the state of each digital output, you can define frames of any bit width (10, 12, 16, 32, or more) and clock each bit out at a precise, configurable rate.

This technique can also serve as the foundation for building a full UART style communication scheme if your application requires start/stop bit framing, parity, and standard baud rates, however this article does not expand on this approach.

Steps:

1. Create a new FPGA VI in your project. On the block diagram, place a Single Cycle Timed Loop clocked at the FPGA default clock (for example, 40 MHz). Inside the loop, create a Case Structure driven by a state enum. Define the following states: Init, Idle, Write Data Bit, and Close.
2. In the Init state, calculate the number of FPGA clock ticks per bit. Use a Quotient & Remainder function to divide the FPGA Clock Rate (40000000) by the Baud Rate (9600) and store the result in a shift register called One Bit (U32). This produces a value of 347 ticks per bit, which can be used to calculate the ticks per bit rate, in this example a constant of 347 is used. Create shift registers for Data Byte (UX, the data word to transmit), Start (Boolean, transmission trigger), and Data (UX) that needs to be sent over (Ux, initialized to 0). The Input Node and Output Node terminals on the left and right sides of the loop provide connectivity to the host or calling VI. Set the default next state to Idle.
   
3. In the Idle state, monitor the Start Boolean shift register. When Start becomes TRUE, the Select function routes the state to Write Start Bit and passes the Data Byte value through. When Start is FALSE, the state remains in Idle. No data is modified in this state; it simply waits for the trigger.
4. The Write Data Bit state is the core of the transmitter. An Address Counter shift register (initialized to 0) tracks which bit of the Data Byte is currently being output. The Tick Count Quotient & Remainder shift register counts FPGA clock ticks. When the tick counter reaches 0 (meaning one full bit period of 347 ticks has elapsed, checked by the Equal To 0? comparison), the current bit is extracted from the Data Byte using the Number To Boolean Array function and Index Array at the current Address position. The result is written to the Output Element Boolean indicator, which represents the digital output line. The Address is then incremented by 1 using the Increment function and passed through a Select gate. A Counter Value (U32) indicator tracks the overall tick count. When the Address equals the total number of data bits (checked by the Equal? comparison), the state transitions to Close. Otherwise it remains in Write Data Bit and shifts out the next bit.
5. In the Close state, you end the loop.
6. To change the number of bits transmitted per frame, modify the data type of the Data Byte shift register. For example, change it from U9 to U12, U16, or U32. The Address Counter comparison in the Write Data Bit state automatically adapts because it checks against the width of the data type. No other changes to the state machine logic are needed, to achieve the simple transmit.
7. Wire the Output Element Boolean to a Digital Line Output node corresponding to your physical DIO channel.

Result:

The FPGA transmits and receives serial data at any bit width you define, bypassing the 8 bit limitation of standard NI serial modules. The bit rate is precise and fully configurable through the tick counter value.

Next Steps

To build a full UART style frame around this transmitter, add logic like Start Bit Stop bit and a Wait bit for every cycle according to UART protcol.