CI.Period Measurement Difference Between PCI‑6602 and PCIe-6612

When using a CI.Period task to measure the period of a digital signal, I observe different behavior depending on the hardware:

• On the PCI‑6602, the first CI.Period sample often returns a partial period (for example, a smaller tick count like ~8,000–9,000 ticks), because the counter latches the first available edge even if the cycle has not completed.
• On the PCIe‑6612, the first CI.Period sample always corresponds to a full period, and the initial partial interval is not returned.

This difference can affect applications that rely on the partial first period for time‑alignment or synchronization.

The 6602 used an older architecture and ASIC called the TIO. That IP was used in most M Series devices as well. Starting with the STC3Lite with the bus-powered M Series USB devices and in the STC3 proper for X Series devices, a capability was added to ignore that "bad" sample. All devices that use those (or newer) architectures, always enable the capability to remove that data. There is no mechanism to disable it.

The difference in behavior originates from changes in the counter ASIC architecture:

• The PCI‑6602 is based on the older TIO (Timing I/O) ASIC.
  • TIO latches the first available period value immediately, even if only one edge has occurred.
• The PCIe‑6612 is based on the newer STC3 timing engine (also used in X Series and newer M‑Series USB devices).
  • STC3 includes internal logic that identifies and removes incomplete first measurements from CI.Period tasks.
  • This filtering behavior is always enabled and cannot be disabled.

Because this filtering is built into the STC3 hardware and not exposed through NI‑DAQmx, there is no method to revert to the older TIO behavior.