Compatibility of Simulink Auto‑Pipelining with the HDL Coder Support Package for NI FPGA Hardware

Issue Details

I'm trying to reuse my existing Simulink models using the HDL Coder Support Package for NI FPGA Hardware. These models rely on Simulink’s auto‑pipelining features, and I want to ensure they work correctly when generating an FPGA bitfile using the NI FPGA Bitfile Generation workflow. Does this workflow support Simulink’s auto‑pipelining, or does it override those settings?

Solution

The HDL Coder™ Support Package for NI FPGA Hardware provides a specialized workflow called the NI FPGA Bitfile Generation workflow. This workflow is derived from HDL Coder’s standard IP Core Generation flow but extends it to integrate directly with the NI LabVIEW FPGA toolchain.

The NI FPGA workflow enables the following capabilities:

• Generation of a LabVIEW FPGA project directly from a Simulink HDL model.
• Automatic import of the generated HDL IP into the LabVIEW FPGA environment
• Mapping of Simulink model I/O to NI FPGA hardware resources such as board I/O and register interfaces.
• Access to LabVIEW FPGA build and compilation settings, including target selection and compile server selection.
• Delegation of the final FPGA compilation (local or cloud‑based) to NI’s compile servers to produce a deployable FPGA bitfile.

Some features available in the generic IP Core Generation workflow are intentionally disabled, because they are not supported within the LabVIEW FPGA toolchain, for example:

• Automatic generation of a validation model
• Bit‑accurate model verification workflows

The workflow is agnostic to the internal implementation of the imported IP. This means that Simulink and HDL Coder optimizations, such as pipelining, resource sharing, and clock‑rate optimizations, remain fully supported. These optimizations influence the generated RTL and can improve utilization and timing performance during synthesis and place‑and‑route.