Solution
In the VeriStand 2023 Q2 release, to improve the VeriStand Engine performance, the new default for the PCL DAQ timing source is Signal From Task(Sample Complete). This default applies to new projects when the timing source is set to Automatic Timing or DAQ Timing. If at least one DAQ device in the System Explorer supports AI Hardware‑Timed Single‑Point (HWSTP), VeriStand automatically uses DAQ timing with “Signal from Task” as the PCL timing source.
In the setup, all DAQ devices support AI HWSTP, and although 6345 is selected as the Chassis master synchronization device, the VeriStand Engine may internally select the 6225 or 6375 as the timing source for the PCL. This internal selection is what leads to the error.
To resolve the issue, manually set the PCL timing source to “DAQ Timing” and choose the 6345 device as the Master DAQ device (the same device used for chassis synchronization).
