Solution
Time Sensitive Networking (TSN)-enabled cRIO controllers allow you to access some timing signals through the FPGA. The specific models are listed below:
- cRIO-9035 (Sync)
- cRIO-9039 (Sync)
- cRIO-904x
- cRIO-905x
If you add one of these devices to a LabVIEW project, the following signals will be available under the FPGA target:

However, none of them correspond to a PPS signal that can be accessed from the FPGA nor routed to a digital output channel.
The available timing-related FPGA signals are described below:
- Time: Represents the current time in nanoseconds since an epoch (a fixed point in time from which elapsed time is measured).
- Time Source: Provides information about where the time is being sourced from. Possible options are:
- None: The time is not synchronized.
- System: The time is synchronized to the system time.
- External: The time is synchronized to the time reference external to the system.
- Time Synchronization Fault: Boolean value that indicates if there is a synchronization error.
- Offset from Time Reference: Represents the offset in nanoseconds from the time reference. If the controller is not synchronized to the external source, this magnitude will be zero.
- Offset from Time Reference Valid: This magnitude indicates whether the offset is reliable. For example, this parameter will be True if the Time Synchronization Fault signal is False.
If you require to generate a PPS signal on the FPGA, you can create one by using the Time signal mentioned above. As a guide, you can use the Time Sensitive Network (TSN) Community VIs Toolkit for LabVIEW available through the VI Package Manager. The toolkit includes a self-contained VI that generates a PPS output and exports it to a digital output channel.
Note: The Time Sensitive Network (TSN) Community VIs Toolkit for LabVIEW is a third-party product that is not directly supported by NI.