Solution
One of the primary applications of reconfigurable hardware based on the Reconfigurable I/O (RIO) technology is the ability to create custom hardware triggering conditions. Using the LabVIEW FPGA Module along with RIO-enabled FPGA Modules, you can quickly and easily create applications that require triggers.
The PXI trigger lines on the chassis backplane can be accessed from a FlexRIO FPGA Module using FPGA I/O nodes and host-side routing configuration. To achieve this, you should do the following.
Reserve and Unreserve the trigger line on the Host
- In your LabVIEW project, use the Invoke Method named Reserve PXI Trigger on the FlexRIO device to reserve the trigger line needed (e.g., PXI_Trig0) before writing to it.
- After sending the trigger, use the Unreserve PXI Trigger Invoke Method to release the line.
- Both Invoke Methods should look as the image below. Ensure you reference the FPGA Module properly using the Open FPGA VI Reference block. Otherwise, the LabVIEW FGPA Module won't show you the Reserve and Unreserve PXI Trigger methods.
Configure the FPGA I/O Nodes
- In the FPGA VI, add an FPGA I/O Node to a timed-loop and select the PXI trigger line (e.g., PXI_Trig0) from the available resources.
- Hover your mouse on top of the signal element inside the FPGA I/O Node and right-click it. Then, configure it with the option Change to Write.
- Write a boolean value (
TRUE then FALSE) to the node to generate the trigger pulse. - Ensure the pulse duration meets the receiving device’s requirements (typically at least two FPGA clock cycles).
- Below is shown how this would look like. This image does not include logic to control the high and low states of the trigger.
