Solution
The jitter and latency observed on the first AO sample are normal for this kind of module. They result from the module’s delta‑sigma ADC design and are not caused by NI-DAQmx, the programming environment, or the chassis. This design inherently introduces up to one sample clock period of jitter.
This behavior is expected due to its delta‑sigma ADC architecture. Modules that use a resistor‑divider ADC with an update pin allow NI-DAQmx to align the first output sample precisely with a trigger. In contrast, those who use a delta‑sigma ADC are driven by a continuous sample‑clock timebase rather than a discrete update mechanism.
The DAC oversamples at 256 * fs and requires around 130 sample periods to initialize. Because of this long initialization time, NI-DAQmx cannot start the ADC exactly at the trigger without adding a large latency. Instead, NI-DAQmx starts the ADC early, and the trigger only selects which sample clock period begins the output. This design inherently introduces up to one sample clock period of jitter.
If this delay is unacceptable, consider alternative AO modules like the NI-9263, which do not have this delay.