Resetting an FPGA Running a Custom CLIP From LabVIEW FPGA

Issue Details

I am developing a socketed component-level IP (CLIP) for my NI FPGA Module. This socketed CLIP includes a reset type signal. However, when I try to call that signal from the LabVIEW FPGA Module, the CLIP interface does not show me my reset signal. Also, when I try to reset the FPGA using the Reset Invoke Method, I don't see it reliably resetting my socketed CLIP.

How can I resolve this, and what is the proper way to reset my FPGA Module in this scenario?

Solution

You can customize the I/O for your NI FPGA device by using socketed component-level IP (CLIP). Socketed CLIP allows you to add your own VHDL code to a LabVIEW FPGA project to program the FPGA to runt he I/O in the way your application needs it.

When using reset type signals in a socketed CLIP, it is expected that the reset signal does not show up in the LabVIEW FPGA CLIP interface. This happens because these reset type signals are interpreted by LabVIEW FPGA as global reset signals. Therefore, the software doesn't expose the signal as it would be allowing users to double-drive the reset behavior. 

The proper way to connect the socketed CLIP's reset signal to LabVIEW FPGA and get the whole FPGA reset, is by leveraging the global asynchronous reset functionality and using the Reset Invoke Method. However, for this approach to work properly, it is key the user codes the reset signal in the socketed CLIP correctly. For common usage, the reset signal is asynchronous and at a higher priority than the clock process of the socketed CLIP. On a code level, it would look as follows, where aReset is the reset signal:

if aReset then
.....
elsif rising_edge(Clk) then
.....
end if;

By declaring the socketed CLIP's reset signal as a reset type as shown above, the software automatically connects it to the global asynchronous reset method of LabVIEW FPGA, and links the reset command to the Reset Invoke Method. 

Additional Information

Boolean type signals could also be used to drive resets in a socketed CLIP. However, this is highly dependent on the usage and application. If the user wants a separate reset signal to control the CLIP, it should be fine to use a Boolean type to allow it to be toggled manually in LabVIEW FPGA or via external DIO. It is the user responsibility to understand the use cases for whether reset synchronization is required or not.