How to Send and Receive LVDS Signals on Single-Board RIO (sbRIO)

Creating a CLIP with the sbRIO CLIP Generator

1. Enter the CLIP name and select the target type.
   If you enter a description, it will be displayed later in the LabVIEW Properties dialog.
   
    
2. If required, configure a serial port definition. 
3. Define the I/O lines for LVDS communication. The required settings are:  
   
   
   1. I/O Standard: LVDS_25
   2. Direction: Input or Output
   3. Drive Strength: N/A
   4. Slew Rate: N/A
   5. Bank Voltage Level: 2.5 V
4. By default, the I/O standard is set to LVCMOS.
   When changing a digital line to LVDS_25, configure the line with the “_P” suffix. The corresponding “_N” differential pair will automatically be grayed out.

   When LVDS_25 is selected, several warnings may appear:

   • The line is configured as bidirectional. Differential lines must be configured as either Input or Output.
   • The bank voltage is set to 3.3 V. LVDS_25 requires 2.5 V, so the bank voltage must be changed.
   • Warnings for Drive Strength and Slew Rate. For differential signals, both must be set to N/A.

   Once all warnings are cleared, proceed to the next step. 
5. Define the LabVIEW I/O nodes.
   Only the I/O nodes added here will appear in the LabVIEW project. The settings for adding the send port and receive port are as follows:  
   
   
   1. I/O Direction
      • Input port: Read-only
      • Output port: Read/Write
   2. LabVIEW Data Type: Boolean
       
6. Configure clock resources for the CLIP, if required.  
7. Specify the output location for the CLIP and complete the process.
   If successful, the configuration file and VHDL files are generated in the specified directory. 
   
    

Importing the CLIP into LabVIEW FPGA

1. After adding the target to the LabVIEW project, right-click the RMC Socket under the FPGA target and select Properties.
   
2. Navigate to General » RMC Socketed Component Level IP Declaration and load the CLIP configuration (.xml) file created earlier.
   
3. When the CLIP is successfully loaded:

   • The description entered in the sbRIO CLIP Generator appears.
   • The configured I/O nodes appear under the RMC Socket.
   
   
4. Drag the I/O nodes into the FPGA VI to use the RMC DIO ports for LVDS communication.

By dragging the IO node that appears and adding it to the FPGA VI, you can use the RMS DIO port for LVDS communication.