The PXIe-7902 and PXIe-7903 devices are part of the High-Speed Serial family of NI's FlexRIO hardware. These devices are designed for engineers who need high-performance FPGA coprocessing capabilities or who need to validate, interface through, and test serial protocols. The PXIe-7902 device uses a Xilinx Virtex-7 FPGA chip. However, the PXIe-7903 device uses a Xilinx Virtex UltraScale+ FPGA chip. This difference in the FPGA chip is what causes the change in how the reference clocks of the MGT ports are configured.
For the PXIe-7902, the configuration was done on the project level through a Clocking and I/O configuration window. Nevertheless, for the PXIe-7903 it happens programmatically on the host side of the LabVIEW FPGA application with a VI. This is done by using the Clock Property Node of the FlexRIO driver API. The first step is to find this property node by going to the block diagram of your host VI, then right-clicking in any part of the empty blank space and following this path: Instrument I/O » Instrument Drivers » FlexRIO » NI FlexRIO API v1 » Properties » Clock Property Node. Once the property note is placed in the block diagram, it will automatically show the Active User Clock property. You must use this property to tell LabVIEW which clock you are configuring. Below is how the property node looks like when placed in the block diagram:
In the image above, it is configuring the CLK0, which is the reference clock that drives the CLK OUT port in the PXIe-7903. In addition to the Active User Clock property, you must also include the User Clock Frequency property to dictate the frequency you require for the port's reference clock. To do so, hover your mouse on top of the Clock Property Node and wait for the small blue squared dots to show up, then user your mouse to expand the property node so it shows up another property field:
By default, it will show the Bypass PLL property. To replace it for the User Clock Frequency, click it and then hover your mouse on top of User Clock and then click on Frequency:
Then, wire the needed frequency for your reference clock. After that, you need to call the Commit VI of the FlexRIO driver LabVIEW API. That VI can be found at Instrument I/O » Instrument Drivers » FlexRIO » NI FlexRIO API v1 » Configuration » Commit. When adding the error and FPGA session references, your code would look as follows:
Be aware that each port has a given clock index. As mentioned above, the CLK0 index configures the CLK OUT port. Below is a table that shows which clock indices corresponds to each MGT port:
This table can be interpreted as:
- CLK0 = CLK OUT.
- CLK1 = MGT Reference Clock 0 and MGT Reference Clock 1.
- CLK2 = MGT Reference Clock 2 and MGT Reference Clock 3.
- CLK3 = MGT Reference Clock 4.
- CLK4 = MGT Reference Clock 5.
- …
- CLK10 = MGT Reference Clock 11.
It is important to mention that the FlexRIO driver includes examples on how to implement this. More specifically, the Aurora64b66b shipping example for the PXIe-7903 includes a host VI to configure the reference clocks of the MGT ports. To access this example, first open LabVIEW. Then, go to the upper tool bar and click Help. From there, follow this path: Find Examples... » Hardware Input and Output » FlexRIO » Integrated IO » Getting Started » Getting Started FlexRIO Integrated IO.vi. This will open a project creator VI. Inside that VI, named the project and choose where to store it. Then, search for the High Speed Serial section and click on the PXIe-7903 (VU11P) - Aurora option. Finally, navigate to the folder where you stored the project files. From there, follow this path: Utilities » Host » Public » 7903 Reference Clock Config.vi.