Solution
The PXle-7903 is designed for engineers who need high-performance FPGA coprocessing capabilities or who need to validate, interface through, and test serial protocols. It includes a Xilinx Virtex UltraScale+ FPGA that has 20 GB of DRAM memory onboard divided into two banks of 10 GB each. The PXIe-7903 DRAM interface operates at 1333 MHz internally. However, LabVIEW FPGA exposes a 333 MHz DRAM base clock.
Even with LabVIEW FPGA exposing the 333 MHz clock, you are not limited to using only this 333 MHz clock for DRAM interactions. In LabVIEW FPGA, you can instantiate DRAM nodes in any available clock domain. When you do this, LabVIEW automatically inserts clock domain crossing FIFOs to transfer data between your chosen clock and the DRAM clock. This means you can use derived clocks or other clocks in your design to drive DRAM operations. For frequency ranges, you are not strictly limited to 333 MHz. You can use slower or faster clocks depending on your design requirements. However, the actual data transfer rate is governed by the DRAM interface timing and the efficiency of the FIFOs LabVIEW inserts.
It is important to mention that using multiple clock domains introduces latency and throughput considerations. Ensure your design accounts for these factors when crossing clock domains.