PXIe-6674T Clock Generation and Routing Capabilities via PFI

Updated Aug 12, 2025

Reported In

Hardware

  • PXIe-6674T

Issue Details

Can the NI PXIe-6674T generate and route clock signals through PFI with flexible clock rates? Is it possible to output multiple different clocks to PFI? What are the limitations and how flexible is it?

Solution

Yes, the NI PXIe-6674T can generate and route multiple different clock signals through PFI channels, but there are some limitations to consider:

  • For applications requiring 4 clock channels, you need to use PFI 0–4. LVDS-type PFIs cannot be used in this case because each board only supports 3 LVDS channels.
  • Clock frequencies can be flexibly configured using the DDS settings.
  • Clock signals are generated and routed via the Sync Clock, which is derived from the DDS output and further divided using two configurable dividers.
  • Supported divider values include: 2, 4, 8, 16, 32, 64, 128, 256, and 512.

 

Example Configuration:

  • DDS = 5 MHz
  • PFI0 (Yellow) = 5 MHz (no division) → Period T = 200 ns
  • PFI1 (Blue) = 5 MHz ÷ 2 (Divider 1) = 2.5 MHz → Period T = 400 ns

​In summary, the 6674T offers flexible clock generation capabilities, but the number of available PFI channels and divider settings must be considered when designing your system.

PXIe6674T SyncClk