Solution
The Single-Cycle Timed Loop (SCTL) is a special use of the LabVIEW Timed Loop structure. Timed Loop structures are always SCTLs when used in an FPGA VI. When used with an FPGA target, this loop executes all functions inside within one tick of the FPGA clock you have selected.
There is no specific limitation for the number of SCTLs running in an FPGA VI. The limitation will be bounded by the FPGA resources and to whether the compiler can resolve the design in the hardware fabric.
The general recommendation given to FPGA programmers is try to design their FPGA VI in such a way where everything, or at least the majority of the code, is put together in the same SCTL. This is because this method will help reduce the use of resources in the FPGA. However, there are a couple of reasons why an FPGA programmer would want to use separated SCTLs:
- Task Separation — A good programming practice is to map logically separate tasks into independent loops when possible, which eases the maintenance and readability of the code. When architected this way, loops take on the role of independent processes, which leverage FPGA parallelism for concurrent operation. Multiple processing loops may act on the same data streams, so it is important to understand the performance implications of passing data between them.
- Forced clock domains — Certain FPGA constructs can be used only in specific clock domains, which forces parts of your application to be in a specific clock domain. This is typically the case when applications interact with components external to the FPGA, such as I/O or DRAM. An application that reads from a high-speed input source and streams the data to DRAM is forced to have at least two loops: one for input and another to write to DRAM. This, in turn, requires a communication mechanism between the loops.
- Clock-domain optimization — When specific I/O constructs force you to use a specific clock domain, you need to know that the rest of the processing tasks may be placed in other clock domains. For example, after averaging or decimating a data stream, you can work with a lower throughput stream, meaning that you might be able to clock downstream functions at lower rates. The lower rates help reduce compile times and resource use as well as increase the odds of a successful compilation.
- Different loop types — Finally, you might use different loop types throughout your FPGA design. Not every part of an application requires the performance benefits of the SCTL. As a result, you might decide to split your application into multiple loops to avoid the relatively more strict requirements of the SCTL. However, separating your application into multiple loops can introduce data-communicating challenges.