Solution
PXI-6683H: Synchronizing to External Time References
The PXI-6683H can synchronize to external time references such as GPS, IEEE 1588 (PTP), or IRIG-B. When this happens, the module disciplines its internal TCXO (Temperature Compensated Crystal Oscillator) to align with the external reference. This results in a highly accurate and stable timebase.
However, this disciplined TCXO does not automatically influence the PXI chassis’s internal backplane clocks (10 MHz or 100 MHz). To propagate this accuracy to the entire system:
- The 10 MHz output from the PXI-6683H’s ClkOut port can be connected to the chassis’s “10 MHz Ref In” port.
- This allows the chassis to use the 6683H’s disciplined clock instead of its own OCXO.
- It’s important to note that the chassis OCXO does not lock to the external clock—it is simply bypassed.
PXIe-6674T: Locking to a Disciplined Clock
An alternative approach involves using the PXIe-6674T, which features a PLL (Phase-Locked Loop). Here’s how it works:
- The 10 MHz signal from the PXI-6683H is routed to the PXIe-6674T.
- The 6674T locks its internal OCXO to this signal using its PLL.
- For successful locking, the input clock must have an accuracy of 1.5 ppm or better.
- The PXI-6683H provides 1 ppm accuracy when calibrated, making it suitable for this purpose.
Once locked:
- The PXI_CLK100 backplane clock is driven by the 6674T’s OCXO.
- This means the entire PXI system benefits from the external time reference’s accuracy and stability, indirectly via the 6683H.