How Do I Set the Power-Up States of My 78xx R Series Device?

Updated May 15, 2025

Reported In

Hardware

  • PXIe-7820
  • PCIe-7820
  • PXIe-7822
  • PCIe-7823
  • PCIe-7822
  • PCIe-7825
  • PXIe-7821

Software

  • LabVIEW FPGA Module

Driver

  • NI R Series Multifunction RIO

Issue Details

I would like to set the DIO lines of my 781xR or 783xR to a given state upon power-up. How do I do this? Do I need LabVIEW to do this ?

Solution

As the manual for R-series devices describes, the DIO lines are high impedance upon startup. Yet, all the DIO lines on the device are likely to have a user-defined power-on state. This can be done by creating an FPGA VI and set the device to both load and run this VI at startup.

If you don't have LabVIEW installed on your machine but you do have the appropriate bitfile, you can use the RIO Device Setup utility to configure your target, as stated below, starting at step 5.
To have the R-series device load and run a VI at startup, do the following:

  1. Create a new project in LabVIEW.
  2. Add your R-series FPGA target to the project.
  3. Create a FPGA VI that sets the initial values of the DIO lines.
  4. Create a FPGA compilation build specification with the Run when loaded to FPGA option checked.
  5. Open the RIO Device Setup utility found in Start » All Programs » National Instruments » NI-RIO. The utility is also accessible by right-clicking the FPGA target in the project explorer, selecting RIO Device Setup.
  6. In the Device Settings tab, select Autoload VI on Device Power Up and click Apply Settings.
  7. Load the VI onto the flash memory. To do this, you can either go to the Download Bitfile to Flash tab of the RIO Device Setup dialog box or right-click on the VI in the Project Explorer window and select Download VI To Flash Memory.
  8. Now every time you reboot, the FPGA will load and run the VI, which will set the values of the DIO lines of the R-series board.

Additional Information

Typically your FPGA VI will do more than just set the initial state of your DIO lines. Thus, you can put the initialization of the DIO lines in the first frame of a sequence structure and the rest of your FPGA VI in the next frame.