Potential Noise Transferring Through MGT Lanes in PXIe-6593

Issue Details

I am planning on using the Digital I/O pins of the DIO port in my PXIe-6593. However, I am also planning on connecting the Multi-Gigabit Transceiver (MGT) lanes of the QSFP+ ports of this card to my Device Under Test. I am concerned that if I use the MGTs of the QSFP+ ports, I might introduce noise into the MGTs of the DIO port, and affect the connection to the other I/O pins of the DIO port. Can this happen?

Solution

The PXIe‑6593 is designed for engineers who need to validate, interface through, and test serial protocols. It includes a Xilinx Kintex Ultrascale FPGA to implement various high-speed serial protocols, and it is programmable in LabVIEW FPGA for maximum application-specific customization and reuse. The PXIe‑6593 takes advantage of FPGA MGTs for up to eight TX and RX lanes within the main QSFP+ ports, and up to four TX and RX lanes in the DIO port.

These MGT lanes are completely separate from each other, meaning that the MGT lanes in the QSFP+ port 0 are different form the ones in the QSFP+ port 1 and are also different from the ones in the DIO port. Therefore, there won't be any crosstalk between the different ports.

Additional Information

Given the hardware architecture used in the PXIe-6593 and PXIe-6594, the same applies to the latter.