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How to Implement an FIR (Finite Impulse Response) Filter in LabVIEW and LabVIEW FPGA

Updated Dec 30, 2024

Environment

Hardware

  • PXIe-5763

Software

  • LabVIEW
  • LabVIEW FPGA Module

The FIR (Finite Impulse Response) filter is commonly used in test and measurement applications to remove specific frequency components. While FFT (Fast Fourier Transform) can be used for data conversion into the frequency domain and filtering data sets, it is not suitable for real-time data filtration during measurements. In such cases, an FIR filter is necessary. This guide provides a brief explanation of the FIR filter principle and its implementation in LabVIEW and LabVIEW FPGA.

Principle of FIR Filter

An FIR filter operates through a combination of addition and multiplication functions. When examining the FFT spectrum for a single peak (Fig. 1), it contains all frequency components equally (Fig. 2). For instance, a high-pass filter removes certain low-frequency components, resulting in a frequency spectrum devoid of low-frequency elements (Fig. 4). In an FIR filter, using an appropriately filtered spectrum and converting it back to the time domain, the waveform resembles a small wave (Fig. 3).

f1.png

This indicates that a high-pass filter can be applied by multiplying the small wave with each data point of the original time-domain data and summing them. This is the basic principle of the FIR filter.

 

Implementing FIR Filter in LabVIEW

To manually apply an FIR filter, you need to create a set of coefficients to manipulate the original time-domain data points. These coefficients are typically called "taps." In this example, we use 13 taps to perform the FIR filter (Fig. 5). The taps are derived from the small wave obtained in Fig. 3. Applying these taps to a waveform in the time domain produces the same filtering effects as its original frequency-domain spectrum (Fig. 6), since the taps are created by the inverse FFT of the frequency-domain spectrum.

f2.png

For example, we apply the FIR filter using Filter.vi in LabVIEW or through manual calculation using the taps shown in Fig. 5.

f5.png

The target data contains three sine waves plus white noise, specifically 10 Hz, 200 Hz, and 450 Hz sine waves (Fig. 7 and 8). Examining the frequency-domain data of the FIR filter (Fig. 6), we observe the absence of the 10 Hz component, a 50% reduction in the 200 Hz component, and no effect on the 450 Hz component. Therefore, this FIR filter effectively removes the 10 Hz component and attenuates the 200 Hz component by 50%. The Filter.vi (blue) and manual FIR filtering (red) are applied as shown below. You can find the Filter.vi in Signal Processing > Waveform Conditioning > Filter.

f3.png

The results show that the 10 Hz component disappeared, and the 200 Hz component was reduced by 50%. In this VI, the manual method is applied to a data set, but it is crucial that this calculation can be done for each data point individually, allowing real-time monitoring of the results (more detailed explanation and figures will be available in the FPGA section).

 

Implementing FIR Filter in LabVIEW FPGA for Reconfigurable Scope and FlexRIO

In FPGA, data points can be acquired and manipulated with very low latency. The FIR filter is often used for filtering each data point. In LabVIEW FPGA, the FIR Compiler is very useful for Reconfigurable Scope and FlexRIO. You can find this function in Programming > Xilinx IP > Digital Signal Processing > Filter. The detailed manual is available on the Xilinx page.

f6 FIR Filter.png

The function performs the following calculation for each data point. The basic calculation is the same as the manual method explained in the previous section. Each data point is multiplied by the taps and summed for each time point. This is an example of FIR filtering for the FPGA reading one data point per cycle.

FIR in FPGA.png

When the FPGA VI reads multiple data points per cycle, the FPGA logic becomes more complex. In an FIR filter, you need to configure it for parallel input by entering the "Input Sampling Frequency" and "Clock Frequency." For example, the NI 5763 reads four data points per cycle at 125 MHz. Thus, the "Clock Frequency" is 125 MHz, and the "Input Sampling Frequency" is 500 MHz. The FIR Compiler automatically calculates the "Number of parallel inputs" as 4. The FPGA size increases with parallel inputs.

Next Steps

Regarding the taps, you need to choose appropriate coefficients. For example, if the edge at the cut-off frequency in the frequency-domain spectrum is too steep, the signal will spread across the entire time domain. Additionally, embedding an FIR filter into an FPGA often requires a deep understanding of both FPGA technology and filter design.

fx.png

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