Solution
To use FPGA designs for the Ettus USRP X410 with NI-USRP 2024 Q4, such designs need to include the FPGA CLIP (Component Level IP) for the RF Daughtercards, even if these CLIP resources are not used by the FPGA design. Failing to do so will result with FPGA load error code -52003, even if the FPGA bitfile generation was successful.
After this error occurs, the USRP X410 requires that a new default FPGA bitfile is downloaded before bitfiles dynamically can be updated via NI FPGA tools. Downloading a new default FPGA bitfile requires use of UHD command line tools using the following steps:
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On your host PC running Windows 10 or later, select Start » Windows System » Command Prompt to open the Windows Command Prompt.
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To print information about your device, run the commands cd “C:\Program Files (x86)\National Instruments\NI-USRP\utilities” then uhd_find_devices.exe
Information about your device is output in the command prompt window, as shown in the following example.
claimed: False serial: 32190B5
Note the line fpga: n/a indicating that no FPGA is loaded.
Use the IP address following addr: to identify your device in the next step.
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Download a new, default FPGA bitfile that uses the PCIe connection, run the commands:
cd “C:\Program Files (x86)\National Instruments\NI-USRP\utilities” then uhd_image_loader.exe --args addr=10.89.8.21,type=x4xx --fpga-path=..\images\X410ReferenceFpga_4ch_4spc.lvbitx
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Reboot the host computer
Note: Failing to reboot the host computer will result in the error code -63150 being reported.
To make an existing FPGA design, that does not already use the RF Daughtercard CLIP compatible with NI-USRP 2024 Q4, please follow these steps:
Note: This workaround is also required when using the following installed project templates:
And requires building an FPGA bitfile after applying the workaround, because the installed default bitfiles for these projects are not functional (will result in the stated FPGA load error).
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Add the RF daughterboard CLIPs as ‘Component Level IP’ to the USRP X410 FPGA target
Add both CLIPs from C:\Program Files\NI\LVAddons\niusrprio\1\Targets\NI\FPGA\USRP\X410\CLIP\RF2x2_100M_CLIP
2. Assign added CLIP whose name ends with _ClipDb0.xml to Daughterboard 0
3. Assign added CLIP whose name ends with _ClipDb1.xml to Daughterboard 1
4. Save Project and Build FPGA