Break Out Options for the PXIe-6569

Issue Details

I want to develop digital communication applications using a PXIe-6569. One of my requirements is to access the pins individually to provide further features to my test system. For example, using an external clock to drive my acquisitions. However, I am confused about the options for the device. I found a terminal block model TB-6569, but it seems it uses a mini-SAS interface. Is there a way to break out the port to a signal level?

Solution

The PXIe-6569 provides a digital I/O interface along with a user-programmable FPGA for flexibility to fit a variety of interfacing and application needs. The board uses a SAMTEC SEARAY™ connector to access its I/O. 

To access the pins on a signal level, you must use the terminal block TB-6569 along with the Mini-SAS HD Breakout Cable to 16 SMA. This combination allows you to access each port separately through an SMA connection. Keep in mind the TB-6569 uses a total of 10 Mini-SAS HD Breakout Cable to 16 SMA connection in order to access all the different signals.