Solution
This is happenning since we are working with FPGAs and not plane software development, then those connectors will have a route at the level of the FPGA code and it will mapp with the VHDL code, so it is not the same creating a generic FPGA I/O constant than intentionally creating a constant for that connector.
For this to work properly you have to start by pulling an I/O node from the project I/O instead of using the FPGA blocks in the pallete. Same goes for creating the constants whereby you must right click on the newly created node and “create constant” for any given input/output instead of using the palatte. Below are step by step instructions:
1.Drag one of the Connectors from the project to the subVI, it will create a FPGA I/O Node for that connector:
2.Then, add a "To Word Integer VI" before the Next Value Indicator and connect the FPGA I/O Node that you created in the previous step:
3. Right-click on the FPGA I/O In Input terminal of the FPGA I/O Node and create a control:

4.Remove the old Input Channel Control and the old FPGA I/O Node, and rename the control:

5.Go to the front panel and link the connector pane terminal by clicking first to the top left corner input terminal and then click on the Input Channel Control:
6.Go back to the FPGA VI and press Ctrl+B to remove all the broken wires:

7.Rigth-click on the Input Channel input terminal of the subVI and select create constant, and take the constant out from the while loop:

8.Remove the old FPGA I/O constants and repeat step 8 for all the while loops.