How to Adjust the DI Read Timing and the Clock Edge Relationship for PXIe-6569?

Issue Details

• What is the relationship between DI read timing and clock edges?
• Can we change the relationship between DI read timing and clock edge?

Solution

SerDes CLIP captures data on both the rising and falling edges, while basic CLIP is for rising edge. We cannot change the relationship of the DI read timing and clock edges. However we can add delays to shift the data.

The delay setting is integrated in the sample project. In host vi and FPGA vi, you can find those settings.
 

Additional Information

The basic procedure to use PXIe-6569 is described in PXIe-6569 Getting Started Guide.. To open the sample program, you need to open LabVIEW. From toolbar menu, please go to Help >> Find Examples..., then you can open NI Example Finder.

On NI Example Finder, you can search sample vi for PXIe-6569 by this procedure. As shown in the figure below, you can find Getting Started FlexRIO Integrated IO.vi under Hardware Input and Output >> FlexRIO >> Integrated IO >> Getting Started.

 

 

You need to select your device and the type of CLIP. It may take 5 or more minutes to open the sample program because it will create relevant files for your settings. When the project is ready, you will get the folder containing all relevant component. Then you can open the project from *.lvproj file. You can find the setting at the host VI as below.

 

Regarding the TX/RX signals in the VI, if the Hex data is 88888888, it is corresponding to 10001000100010001000100010001000. Therefore each DO channels becomes as below.

DO0 = T, DO1 = F, DO2 =F, DO3 = F, DO4 = 1, DO5 = 0,….DO31 = F.

Regarding the settings on the front panel, you can check them by opening context help by Ctrl + H for each functions.