Maximum Frequency of External Clock for DI13 of PXIe-6569

Updated Oct 11, 2024

Reported In

Hardware

  • PXIe-6569

Issue Details

In the sample project for PXIe-6569 (Getting Started FlexRIO Integrated IO.vi), there is an option to use external clock inputted from DI13. What is the maximum frequency?
 
FPGA VI.png

Solution

The SerDes CLIP can handle up to a 625 MHz external clock. The basic CLIP supports up to 150 MHz. To use external clock from DI13, you need to select appropriate clock.
 
ClockConfig.png

Additional Information

The clock is divided by 4 though, so the LabVIEW diagram will see a 120 MHz clock if you input 480 MHz clock. This is done to match the clock speed with the serialization/deserialization ratio.

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