Solution
The PXIe-6592 cannot compile without certain Socketed CLIP elements that are in the example.
Socketed CLIPs are CLIPs which access the IO of the card. For example, FlexRIO uses it to access the adapter module IO and Integrated FlexRIO for accessing the IO.
If a CLIP that isn't used in the design is included in the project, Vivado will still compile its VHDL, which can lead to errors. Disabling unused CLIPs may resolve this.