Issue Details
I have a sbRIO FPGA target and created a VI under FPGA Target. If I put AO FPGA I/O node on the block diagram, I see that it requires data type FXP 20.5. At a hardware level, after the FPGA target that data needs to be sent to the 16-bit DAC of the sbRIO. But 16-bit DAC requires 16-bit data type, so there should be an internal scaling that converts data types from FXP 20.5 to FXP 16 bit. Is there a way to avoid that scaling?