Characterizing Setup to Account for Delay on Digital Trigger

Updated Jun 26, 2024

Environment

Hardware

  • PXIe-5172

When using a digital trigger with the PXIe-5172, there's a delay between when the trigger is received and when the data is acquired. This signal delay is caused by the longer signal path for the incoming signal. The trigger pulse travels a much short path through the module, causing the module to start acquiring before the signal of interest has made it to the ADC. Using the trigger delay property node will delay the digital trigger to account for this signal path.
It is important to acknowledge that this delay varies and has a minimum time of around 600ns and it is something expected for the PXIe-5172, so it is naturally not an error from the hardware but a condition to tune up with a trigger delay if an application can't withstand a delay on the order of nanoseconds.

Required hardware:

  1. PXIe-5172
  2. NI Mini-HDMI breakout cable to 6 BNC (Part number 786979-01)
  3. BNC to SMB adapter

Steps:

  1. Connect Mini-HDMI breakout cable to mini-HMDI port on the PXIe-5172.
  2. Connect breakout cable PFI0 BNC connector to an SMB adapter.
  3. Connect SMB adapter to CH0 input of the PXIe-5172.
  4. Run a data acquisition/data logging vi to measure the digital trigger delay, either numerically or graphically
  5. Use the Trigger Delay property in your own code or in the Time Stamp Trigger. vi application in LabVIEW and write the observed trigger delay from step 4.

The trigger delay feature will account for the delay. It will characterize the setup and apply the trigger. This means that the hardware is commanded to wait a set time whenever it detects a trigger signal before performing the triggering action. It is important to note that this delay will not occur when using an analog reference trigger. This because analog triggers follow the same path as the analog signal whereas digital triggers follow a different short path. Thus, analog signals and triggers will be synchronized. 

The following example shows the Time Stamp Trigger. vi accounting for a 638ns delay and thus synchronizing a digital trigger with an analog signal.

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It is important to acknowledge that a jitter offset of up to 5ns is still possible to happen after the trigger delay correction. This jitter is physically inherent to the hardware and setup. 

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