Solution
The PXIe‑7820 is a reconfigurable I/O (RIO) device that features a user-programmable FPGA for onboard processing and flexible I/O operation. With LabVIEW FPGA, you can individually configure the digital lines as inputs, outputs, counter/timers, PWM, encoder inputs, or specialized communication protocols.
The specifications of the PXIe-7820R explain the Bus Interface of the device has a form factor of x4 PXI Express, specification v1.0 compliant. PXI Express v1.0 lanes have a theoretical data rate of 250 MB/s. Since this device has a by-four form factor and knowing that PXI Express v1.0 dedicated lanes per the direction of communication, that would be a theoretical 1 GB/s data rate between the host and the target.
However, achieving theoretical data rates is rarely the case. In practice, there are two general approximations to put in perspective the real data rate of communication buses. A general rule of thumb is that the bus will have 80% of the theoretical value (800 MB/s for this board). This is valid when the interest is guaranteeing sustained data rates. However, this is different than average or peak data rates. Our x4 PXI Express v1.0 products can do closer to 90% (900 MB/s for this board) for average and peak rates.
It is imperative to understand that the rates discussed above assume an application that is transferring data over direct memory access in an optimized system. Nevertheless, when operating at the edge of those data rates, many things could affect the performance. For example: FIFO depths, buffer sizes, CPU utilization, BIOS settings, depth of the PCIe tree, competing simultaneous traffic in the same device or other devices, etc.