Slice Use of FPGA Resources in LabVIEW FPGA Module

Updated Sep 8, 2023

Reported In

Hardware

  • CompactRIO Single-Board Controller
  • sbRIO-9637

Software

  • LabVIEW
  • LabVIEW FPGA Module

Issue Details

I have compiled a LabVIEW FPGA Module project for my Single-Board RIO 9637 (sbRIO-9637). The Compilation Status window shows the Final Device Utilization (Placement) report pasted below where I can see the resources used. I can see I have used 38.1% of the Slice Registers and 69.7% of the Slice LUTs. However, the report shows I have consumed 95.6% of the Total Slices available. How are Slice Registers and Slice LUTs related to each other and to Total Slices, and how are the percentages related between the resources?
 
Compilation Status Report.png

Solution

The FPGA resources available in a chip and how they interface with each other depends on the chip manufacturer. NI's devices use Xilinx FPGAs and each Xilinx FPGA family has a different architecture for how a slice is composed.

The Single-Board RIO 9637 (sbRIO-9637) has a Xilinx Artix-7 Zynq 7020 FPGA that uses 4 LUTs and 8 flip flops to create an FPGA slice. It has a total of 13300 slices, which means it has 53200 LUTs and 106400 flip flops. The Final Device Utilization (Placement) report uses the word Registers to present the flip flops resources, but other than that, the report shows the expected resources values for the sbRIO-9637.

However, the fact that an Artix-7 slice is composed of 8 flip flops and 4 LUTs doesn't mean the compiler will use the resources efficiently. The compiler has constrains it must follow, but if a design satisfices the constrains, it will use the resources as required without necessarily optimizing the use. For example, if 8 flip flops are required, the compiler could use the 8 ones available in a slice and only consume that. Nevertheless, it could also use 4 flip flops per slice and consume 2 slices, or 2 flip flops per slice and consume 4 slices.

If needed, NI recommends ways to optimize FPGA code. To cover this topic, visit the documents How Can I Optimize FPGA Resource Usage or Speed?Optimizing FPGA VIs for Speed and Size (FPGA Module), and Optimizing FPGA Compilation for Area or Speed.

Additional Information

In the article Slices on an FPGA Chip, an extensive explanation of the resources needed for a slice depending on the FPGA family and how NI's devices are mapped between FGA families is given. The information provided in this article was focused on the sbRIO-9637 but if you are using another NI FPGA device, use that article to understand the resources in your FPGA card.