Revise the Default Line Rate of NI PXIe-6593 IP core

The NI PXIe-6593/4 PXI High-Speed Serial Instrument is designed for verifying, interface passing and testing serial protocols. Up to 8 TX and RX channels.

In its specifications document, Its data rate of both serial ports are from 500Mbps to 16.3Gb/s,

In the example project provided in NI LabVIEW, the supplied compiled bitflie is also generated using CLIP files based on this rate.

This article will explain and walk through how to change the default data transmission line rate in CLIP. 

Before taking this task you should get through Generating and Integrating Aurora IP into Your LabVIEW Project

1. Generate a new PXIe-6593 (KU040) - Aurora Streaming example project using LabVIEW example "Getting Started with FlexRIO Integrated IO.vi". (choose project directory based on your own need)

Find the Socketed CLIPs folder in the PXIe-6593 example projects provided by NI, just like shown in the figure below:


2. Refer to Generating and Integrating Aurora IP into Your LabVIEW Project to launch【Vivado.bat】and create a new project.

Select the TYPE of FPGA chip corresponding to FPGA Target Properties in LabVIEW PXIE-6593 sample project, or refer to information tagged on your hardware.



3. In Project Manager, go to SYNTHESIS, right-click Run SYNTHESIS, and select SYNTHESIS Settings. Change the -flatten_hierarchy attribute on the following page from the default "rebuilt" to "None". This is to avoid interface or structure changes with the original IP caused by IP core version updates in later steps, which may cause new support file is incompatible with the original VHDL code.


4. In Project Manager, select Add Sources and Add the. xci file, which is the IP core from the LabVIEW sample Project Socketed CLIPs folder. After loading, Upgrade Version is required; otherwise, THE IP address will be locked.



5. After Upgrade is complete, click Generate.
Double-click. xci in Sources Tab to open the IP Core configuration page.

In the CLIP provided with LabVIEW example, we can see the line rate is set to 16.25Gbps, and you can change this value and other configuration properties in this page according to real requirements. In this example, the Line Rate(Gbps) need to be changed to 10Gbps.
Click OK. Click Generate again.


6. Create an EDN file for the new IP core.
Right-click the.xci file in the Sources Tab and select Open IP Example Design. Vivado generates a new project window and automatically names it _DS_ex.

7. In the new project window, repeated the steps in step3, revising "rebuilt" into "none".

8. Select the top-level file and execute Run Synthesis. Wait until the execution in Design Runs Tab completes.


9. After synthesis completed, select Open Synthesized Design, and click OK.


10. Now we can see both the Synthesized Design window and Netlist Tab。


Enter the following command to generate netlist files in Tcl Console:

write_edif -cell aurora_64b66b_DS_block_i aurora_64b66b_DS.edf

After running, a new netlist file will be generated in the corresponding vivado project folder:



11. Use Notepad++ or other text editing software to modify the. xdc file in the Socketed CLIP folder to change line 7 from 16.25 to 10. Save the new xdc file into new CLIP support file folder.


Add the following code on the Line 55:

set_false_path -to [get_cells -hier -filter {NAME =~ %ClipInstancePath%/AuroraBlock.GenAurora[*].Aurora_PortN/*userclk_tx_main.tx_active*_reg}]

set_false_path -to [get_cells -hier -filter {NAME =~ %ClipInstancePath%/AuroraBlock.GenAurora[*].Aurora_PortN/*userclk_rx_main.rx_active*_reg}]



Note: This step is due to an error message during the subsequent compilation process. If your actual situation is different from this article, you can modify the xdc file according to the specific compiler error message in your case.

12. Now we have the updated EDN file and XDC file. Copy the other relevant files into the new CLIP folder. Now we have all the supporting files for the new CLIP.


13. Back to the LabVIEW project file, right-click PXIe-6593 (KU040), select Properties, select Component-level IP, and create a CLIP.


14. Add all the CLIP support files as shown below. Set the correct Top Level VHD file.


Go through the following figures to complete your CLIP settings.








15. After clicking Finish, LabVIEW will generate a new XML file to describe the new CLIP.


16. In the LabVIEW project file, right-click IO Socket, select Properties, and select the updated XML file corresponding to the updated CLIP.


17. Update the code in LabVIEW FPGA VI if necessary, which is not needed in this example.

18. Recompile FPGA VI with the new CLIP to obtain the new bitfile.