To model an AND gate [h3]
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Take you need two inputs and one output pin.
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Define the logic for the unused pins in the table.
Note that when you wire this part, leave those extra pins unwired.
The AND gate output is high only when both inputs are high, all the other input conditions result in a low output. You can define this model using only two conditions, the model is shown below, the bold text indicates the lines that were modified, everything else came from the default model.
+( behaviour= "
+/inputs I1 I2 I3 I4
+/outputs O1 O2 O3 O4
+/table 2 ;must correspond to the number of rows in the table
+; inputs ;outputs
+ 1 1 X X 1 0 0 0
+ X X X X 1 1 1 1
+" )