Error 56 When Using VeriStand FPGA Addon

Updated Jan 7, 2022

Reported In

Software

  • VeriStand Custom Devices
  • VeriStand

Issue Details

I am using FPGA Addon Custom Device for my application but it was having timeout Error 56. How to solve this issue ?

Solution

As mentioned in FPGA Addon Quick Start Guide.md, FPGA code requires an IRQ (address of 30) to control when the FPGA bitfile starts. So you need to add an interrupt with address 30 in front of the FPGA VI, otherwise you will get timeout error 56.

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