Solution
Implicit enable signals are part of the enable chain, which is additional logic that LabVIEW adds to the FPGA codes to enforce dataflow on the FPGA hardware. More specifically, single-cycled timed loops use these implicit enable signals to enforce dataflow inside them. These signals fan out to all nodes within the loop that contain state-holding elements.
LabVIEW does not support the Close and Reset if Last Reference option of the Close FPGA VI Reference function in projects in which implicit enable signals have been removed. Also, the functionality of "
allow removal of implicit enable signals" should only be used if you are using single-cycled timed loops in your code.
If you are using single-cycled timed loops and you do want to allow the removal of implicit enable signals, then you cannot use the Close and Reset if Last Reference option. To change this, follow the next steps:
- Go to the block diagram of your LabVIEW FPGA code.
- Right-click the Close FPGA VI Reference function.
- Select the Close option.
If you are using single-cycled timed loops but you do not want to allow the removal of implicit enable signals, or if you are not using single-cycled timed loops at all, you should disallow the removal of implicit enable signals. To do so follow the next steps:
- Go to your LabVIEW project.
- Expand the Target's content.
- Expand the Build Specifications option inside the Target.
- Right-click your build.
- Click Properties.
- Stay inside the Information category.
- Notice the checkboxes in the middle of the screen.
- Uncheck the box that says Allow removal of implicit enable signals inside single-cycle Timed Loops.
After unchecking the box and recompiling the VI, the error should disappear.