Add Custom FIR Filter in FPGA of Reconfigurable Oscilloscope

Updated Mar 24, 2022

Environment

Hardware

  • PXIe-5172
  • PXIe-5171
  • PXIe-5170
  • PXI FlexRIO Digitizer

Software

  • LabVIEW
  • LabVIEW FPGA Module

Driver

  • LabVIEW Instrument Design Libraries for Reconfigurable Oscilloscopes

One of NI’s strengths is flexibility in the application based on FPGA. In Reconfigurable Oscilloscope, NI provides the FPGA source code to the customer for more flexible development.
With this strength, users can use this Reconfigurable Oscilloscope in many applications such as monitoring applications with custom triggers, IF applications, and other applications which need FPGA. In these applications, various ranges of digital filters are needed.
This article includes the steps of creating a custom 40MHz FIR filter in Reconfigurable Oscilloscope FPGA and setup parameters in Host. This article can help to create a variety of custom FIR filters in a Reconfigurable Oscilloscope and other FlexRIO FPGA environments.

Create Project

  1. Open LabVIEW "File >> Create Project".
LabVIEW.PNG
  1. On Create Project window,  Create the example "Oscilloscope >> Multirecord Acquisition (NI5170)".
Project.png
  1. Choose the right example based on hardware.
  2. In the sample project, Open Multirecord Acquisition (FPGA).vi in the FPGA tree. In the block diagram, the red box indicates the 'FIR filter.vi' which is placed after the 'Digital Correction.vi'.
FPGA_VI.PNG
  1. Inside of that, there is a Single Channel FIR Filter.vi in the block diagram
  2. Open the Single Channel FIR Filter.vi block diagram. Inside of the Single Channel FIR Filter.vi, there are FIR filter functions ‘Parallel Non-sym FIR – 2 spc – 2x oc – 15 coef.vi’.FPGA_VI_Filter.PNG
  3. The parameters such as filter select, coef load, coef write, and coef data are shown.
1.PNG
  1. For custom use, the new coefficient should be created for the new filter range.
  2. Disconnect and delete the existing filter coefficients control and create a new control.
3.PNG
  1. Connect the terminal connecter pane in the front panel icon from this VI to the top-level VI for the host configuration.
2.PNG
  1. Connect the terminal until 'Filter Coefficients Control' is created on the Top level FPGA VI.
4.PNG
  1. Compile the FPGA code.
cpi.PNG

Create New Coefficients

  1. For custom filters, new coefficients are needed. In the host, create a new VI for new coefficient creation. Put the ‘FIR Windowed Coefficients.vi’ in the block diagram which is located in "Function Pallete >> Signal Processing >> Filters >> Advanced FIR >> FIR Win Coef".
Filter_Coefficient.PNG
  1. Set the sampling freq, filter type, cutoff freq, and taps. Then run the vi for the coefficients.
  2. Check the coefficients are created. taps are the number of coefficients.
hostfrontpanael.png

Setting and Apply Custom Filters

  1. After the compilation is done, In the main host 'Multiple Record Fetch (HOST).vi', create the FPGA Read/Write Control function and select the filter coefficients.
  2. For applying new coefficients, the load and write coefficients process is needed. Refer to the code down below. Apply_Coeff.PNG
  3. Write the new coefficients for the custom filter.
  4. Check the load order of the coefficients, to ensure that the filter has the right setup because each filter has its own order according to the sample per cycle. See the detailed explanation of the filter.
  5. Run the new filter example and check the result of the filtered signal.
The other filters are located in <Program Files>\National Instruments\LabVIEW 2020\instr.lib\_niInstr\DSP\v1\FPGA\Public\Sub VIs\EqParallel.

In conclusion, this article explains how to use an FPGA filter in an easy way.