TestStand Test Time Is Too Long When Configuring a DDS Frequency

Updated Dec 9, 2021

Issue Details

I am working with TestStand and the Semiconductor Module to develop a test sequence. My sequence uses a timing card that generates a clock frequency using DDS and outputs the clock. The step that configures the timing card takes too much time. Is it possible to reduce the module time for this specific step?

Solution

The expected time for the timing card driver to generate the requested frequency using DDS is around 750ms. An additional 3ms have to be taken into account for the routing of the generated clock to the ClkOut output of the timing card.

In a Semiconductor test framework, it is best to initialize and configure any step that takes significant time in the Process Setup sequence to avoid the module time impacting the actual main test.

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