Simultaneous Read From Multiple Memory Addresses in SCTL Using NI LabVIEW FPGA

Updated Jun 11, 2023

Reported In

Software

  • LabVIEW FPGA Module

Issue Details

In my NI LabVIEW FPGA application, I need to read from multiple addresses of BRAM memory simultaneously in a single-cycle timed loop (SCTL). What is the best way to accomplish this?
 

Solution

Simultaneous reading from multiple addresses of BRAM memory in an SCTL is not possible. Depending on the arbitration mode selected in the Memory Properties>Interfaces page, this may cause an error at the compilation stage or result in corrupted data if a compilation was successful.

The only exception is if you initialize the memory resource (on the Initial Values page of the Memory Properties) and configure the Interface B of the memory resource for 'Read' (on the Interfaces page of the Memory Properties). This will turn the memory resource into read-only memory (ROM), with two read ports (instead of the default single read port and a single write port). With this, two simultaneous reads will be possible. However, there will be no provision to overwrite the initial memory data.
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Additional Information

The best way of achieving simultaneous data read/write from/to memory in an SCTL is to define multiple instances (or configurations) of memory in the project (or using VI-defined memory). Reading or writing from/to each separate instance in parallel in an SCTL is possible.
 

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