The phase performance is impacted by several reasons including signal-to-noise (SNR) ratio, LO leakage, and in-band Spurs. At the center frequency, the USRP devices are known to have a significant LO leakage. As the LO leakage amplitude and phase have higher variance, it has an additive impact on the phase and amplitude of the signal as well. However, the impact is significant when the input signal power becomes comparable to the LO leakage power.
To improve the performance degradation because of LO leakage (or any other spur), the contaminant has to be taken out of the band. A typical way of doing it is by digital frequency shift followed by digital filtering or decimation. NI USRP RIO architecture already contains both these IPs in its FPGA code. Refer to the article related to LO leakage suppression
for more details.