Additional Information
When simulating an FPGA VI we need to take into consideration that we're no longer relying on "real" timing but instead, we're working with simulated timing from LabVIEW. LabVIEW does a convention to approximate how much time or tick to add to its counter when it runs like this, meaning simulated timing is in no way accurate.
To improve its accuracy, you could use the
FPGA Desktop Execution Node or implement other functions that correct for the error in your FPGA code.